24 Mar 2025, 08:19 UTC≈2,600 views19 reactionsread 6 August 2026 Photo
Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually it is a fixed point fractional divider).
Features
▫️Resulting frequency precision down to the 0.01Hz
▫️calculating PPM error
▫️calculating jitter spec
Links
💾 https://github.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider
📄 https://www.eevblog.com/forum/fpga/verilog-floating-point-clock-divider-release/
#verilog #DIV #FP #…
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Signed Dmitry Murzinov
13 Sept 2024, 11:08 UTC≈3,090 views17 reactionsread 6 August 2026 Photo
fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
This algorithm is fast, since the sorting itself is done in parallel while the data is being input serially. It is sorted and ready to be read back immediately following the last write transfer.
A 256-length, 8-bit sorter costs approximately 5500 logical elements on an Altera Cyclone …
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Signed Dmitry Murzinov
Channel name was changed to «𝗜𝗣 cores»
10 Sept 2024, 17:50 UTC≈2,840 views22 reactionsread 6 August 2026 Photo
FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Motors (PMSM) or Brushless DC Motors (BLDC)
Features
▫️Support 3 channels of PWM + 1 channel of EN
▫️Supports angle sensor and phase current sampling ADC with 12bit resolution
▫️Internally uses 16bit signed integer for computation
Links
💾 https://github.com/WangXuan95/FPGA-FOC
#verilog #BLDC #PMSM #FOC #motor
@ipcores
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Signed Dmitry Murzinov
24 Apr 2024, 11:59 UTC≈3,560 views21 reactionsread 6 August 2026 Photo
Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA
Features
▫️Specifically designed for the 256/512/1024 bit wide AXI4-Stream interface
▫️Generic MSI-X compatible interrupt controller.
▫️Supporting PCIe Gen3, Gen4 and Gen5
▫️Supporting Series 7, UltraScale, Ultrascale+, Versal Prime and Versal Premium FPGAs
Links
💾 https://gitlab.nikhef.nl/franss/wupper/
📄 https://gitlab.nikhef.nl/franss/wupper/-/blob/mast…
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Signed Dmitry Murzinov
9 Apr 2024, 10:18 UTC≈3,110 views17 reactionsread 6 August 2026 Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantissa and exponent.
Features
▫️Fully parametrizable bit widths for exponent and mantissa
▫️Handles all special cases:
▪️ SNaN/QNaN
▪️ ± infinity
▪️ Denormalized numbers
▪️ Zeroes
▫️Single cycle operation
▫️Supports rounding to nearest (per official specification) or simply chopping bits
Links
💾 https://…
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Signed Dmitry Murzinov
23 Nov 2023, 15:42 UTC≈3,900 views15 reactionsread 6 August 2026 Photo
NNgen is an open-sourced compiler to synthesize a model-specific hardware accelerator for deep neural networks. NNgen generates a Verilog HDL source code and an IP-core package (IP-XACT) of a DNN accelerator from an input model definition.
Generated hardware is all-inclusive, which includes processing engine, on-chip memory, on-chip network, DMA controller, and control circuits. So the generated hardware does not re…
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Signed Dmitry Murzinov
20 Nov 2023, 08:13 UTC≈3,200 views13 reactionsread 6 August 2026 Photo
FPnew - New Parametric Floating-Point Unit with Transprecision Capabilities
Operations:
▫️Addition/Subtraction
▫️Multiplication
▫️Fused multiply-add in four flavours (fmadd, fmsub, fnmadd, fnmsub)
▫️Division
▫️Square root
▫️Minimum/Maximum
▫️Comparisons
▫️Sign-Injections (copy, abs, negate, copySign etc.)
▫️Conversions among all supported FP formats
▫️Conversions between FP formats and integers (signed & unsigned) a…
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Signed Dmitry Murzinov
1 Nov 2023, 20:28 UTC≈2,860 views27 reactionsread 6 August 2026 Photo
FPGA-FFT - a highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
Features
▫️Data input/output are continuous with no gaps between frames
▫️Support power-of-two sizes
▫️Support fixed point data
▫️Resource usage is on par with Xilinx FFT IP core
▫️Fmax is up to 30% higher for common sizes than Xilinx FFT IP core
Links
💾 https://github.com/owocomm-0/fpga-fft
#fft #dsp #vhdl #xilinx
@ipco…
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Signed Dmitry Murzinov
19 Oct 2023, 15:32 UTC≈2,770 views15 reactionsread 6 August 2026 Photo
Send video/audio over HDMI on an FPGA
SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.
Features
▫️ 24-bit color
▫️ Data island packets
▫️ Null packet
▫️ ECC with BCH systematic encoding GF(2^8)
▫️ Audio clock regeneration
▫️ L-PCM audio 2-channel
▫️ Audio InfoFrame
▫️ Video formats 1, 2, 3, 4, 16, 17, 18, 19
▫️ VGA text mode
▫️ IBM 8x16 font
▫️ Double Data Rate I/O (DDRIO)
▫️ …
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Signed Dmitry Murzinov
16 Oct 2023, 12:29 UTC≈3,020 views30 reactionsread 6 August 2026 Photo
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.
Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not re…
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Signed Dmitry Murzinov
9 Oct 2023, 16:25 UTC≈2,680 views25 reactionsread 6 August 2026 Photo
FPGA USB-device - USB full-speed device core to implement. It requires only 3 FPGA common IOs rather than additional chips.
Features:
▫️Pure Verilog implementation
▫️Implementation of USB-serial, USB-MSD, USB-camera, USB-audio, USB-hid, etc
▫️The circuit is simple: three FPGA pins, one resistor and one USB connector
💾 https://github.com/WangXuan95/FPGA-USB-Device
#USB #HID #MSD #UVC #CDC #device #verilog
@ipcores
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Signed Dmitry Murzinov
Showing the 12 most recent of 20 posts we hold for @ipcores. View and reaction counts are the latest single reading for each post, not a live figure, and a recent post is still accumulating both. A view count marked ≈ was rounded by Telegram before we ever saw it — t.me prints views in full below 1,000 and to three significant figures above, so ≈1,200,000 means somewhere between 1,150,000 and 1,249,999. Unmarked counts are exact. Text is reproduced from the public post preview and truncated for length.
