27 May 2025, 06:47 UTC≈4,040 views18 reactions6 Starsread 7 August 2026 Photo
Automated SV Assertion Interface Generator:
It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing assertions.
Features
▫️ Automatically detects the top-level module in the design hierarchy
▫️ Extracts ports and registers from the RTL code
▫️ Handles naming conflicts by using hierarchical path…
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Signed Dmitry Murzinov
4 Feb 2025, 14:35 UTC≈5,270 views12 reactionsread 7 August 2026 Photo
A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate …
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Signed Dmitry Murzinov
11 Sept 2024, 08:17 UTC≈5,920 views10 reactionsread 7 August 2026 Photo
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchma…
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Signed Dmitry Murzinov
15 Aug 2024, 16:09 UTC≈5,780 views14 reactionsread 7 August 2026 Video
FloorSet: The First Million-Scale Dataset for SoC Design Planning.
FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 million synthetic benchmark circuits that capture real design constraints and objectives, all carefully sampled from actual design distributions.
FloorSet addresses key challenges of training-data availab…
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Signed Dmitry Murzinov
7 Aug 2024, 09:09 UTC≈4,760 views11 reactionsread 7 August 2026 Photo
This element is a runtime, dynamically reconfigurable, LUT5 that enables the changing of the function of the LUT during circuit operation. Using the CDI pin, a
new INIT to change the logical function.
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Signed Dmitry Murzinov
7 Aug 2024, 09:09 UTC≈4,040 viewsread 7 August 2026 Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5
Note: This component occupies one of the eight LUT6 components within a CLBM.
#UG974 #Xilinx #recongif
Signed Dmitry Murzinov
8 Jul 2024, 11:58 UTC≈4,720 views13 reactionsread 7 August 2026 Photo
The new taste is unlocked: BiCMOS
Now IHP providing not only 𝐨𝐩𝐞𝐧-𝐬𝐨𝐮𝐫𝐜𝐞 𝐏𝐃𝐊 but also 𝐟𝐫𝐞𝐞 𝐚𝐜𝐜𝐞𝐬𝐬 𝐭𝐨 𝐌𝐏𝐖 𝐫𝐮𝐧𝐬 to turn your designs into physical chips. This service is available exclusively for non-commercial projects.
💾 https://ihp-open-ip.readthedocs.io/en/latest/
#IHP #PDK #MPW #BICMOS
@fpgasic
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Signed Dmitry Murzinov
27 Jun 2024, 07:11 UTC≈4,330 views4 reactionsread 7 August 2026 Forwarded from @vlsihub
DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs
https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf
@vlsihub
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Signed Dmitry Murzinov
7 Mar 2024, 08:52 UTC≈5,570 views6 reactionsread 7 August 2026 CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.
Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT
#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic
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Signed Dmitry Murzinov
24 Nov 2023, 08:49 UTC≈6,070 views14 reactionsread 7 August 2026 Photo
Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).
Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3
Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator…
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Signed Dmitry Murzinov
21 Nov 2023, 09:21 UTC≈7,640 views15 reactionsread 7 August 2026 Photo
Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.
Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP
Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SA…
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Signed Dmitry Murzinov
2 Nov 2023, 16:48 UTC≈4,140 views9 reactionsread 7 August 2026 Forwarded from @vlsihub
Generate Compilers from Hardware Models
Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make th…
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Signed Dmitry Murzinov
Showing the 12 most recent of 19 posts we hold for @fpgasic. View and reaction counts are the latest single reading for each post, not a live figure, and a recent post is still accumulating both. A view count marked ≈ was rounded by Telegram before we ever saw it — t.me prints views in full below 1,000 and to three significant figures above, so ≈1,200,000 means somewhere between 1,150,000 and 1,249,999. Unmarked counts are exact. Text is reproduced from the public post preview and truncated for length.